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note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon - sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: for existing customer transition, and for new customers or new appli - cations, refer to the a3992. dmos dual full-bridge pwm motor driver a3974 date of status change: november 2, 2009 deadline for receipt of last time buy orders: april 30, 2010 these parts are in production but have been determined to be last time buy. this classification indicates that the product is obsolete and notice has been given. sale of this device is currently restricted to existing customer applications. the device should not be purchased for new design applications because of obsolescence in the near future. samples are no longer available. last time buy
description designed for pulse width modulated (pwm) current control of two dc motors, the a3974 is capable of output currents to 1.5 a and operating voltages to 50 v. internal fixed off-time pwm current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current- decay modes. independent enable input terminals are provided for use in controlling the speed and torque of each dc motor with externally applied pwm control signals. synchronous rectification circuitry allows the load current to flow through the low r ds(on) of the dmos output driver during the current decay. this feature will eliminate the need for external clamp diodes in most applications, saving cost and external component count, while minimizing power dissipation. internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of v dd and the charge pump, and crossover-current protection. special power-up sequencing is not required. the a3974 is supplied in a 44-pin plastic plcc with 3 internally fused pins on each side, for maximum heat dissipation. the fused pins are at ground potential and need no electrical isolation. 29319.35c features and benefits ? 1.5 a, 50 v continuous output rating ? low r ds(on) dmos output drivers ? programmable slow, fast, and mixed current-decay modes ? serial-interface controls chip functions ? synchronous rectification for low power dissipation ? internal uvlo and thermal shutdown circuitry ? crossover-current protection ? sleep and idle modes dmos dual full-bridge pwm motor driver package: 44-pin plcc with internally fused pins (suffix ed) pin-out diagram not to scale a3974 serial port 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 29 30 39 38 37 36 35 34 33 32 31 28 27 26 25 24 23 22 21 20 19 18 dwg. pp-073 gnd gnd logic supply gnd gnd sense 1 out 1a nc strobe clock data gnd gnd ref 1 ref 2 nc out 2a nc sense 2 gnd gnd gnd load supply 2 enable 2 out 2b nc v reg sleep osc gnd gnd cp cp1 cp2 nc out 1b nc enable 1 load supply 1 gnd nc nc nc nc program pwm timer charge pump v dd v bb1 v bb2 logic logic program pwm timer
dmos dual full-bridge pwm motor driver a3974 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 50 v logic supply voltage v dd 7.0 v logic input voltage range v in continuous ?0.3 to v dd + 0.3 v pulsed, t w < 30 ns ?1.0 to v dd + 1.0 v reference voltage v ref 3v sense voltage (dc) v s continuous 0.5 v pulsed, t w < 1 s 2.5 v output current i out output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150c. 1.5 a operating ambient temperature t a range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing A3974SED-T 27 pieces per tube a3974sedtr-t 450 pieces per reel thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja 4-layer pcb based on jedec standard 22 oc/w r jt 6 oc/w *additional thermal information available on the allegro website.
dmos dual full-bridge pwm motor driver a3974 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram copyright ? 2001 allegro microsystems, inc. charge pump bandgap v dd c reg tsd under- voltage & fault detect charge pump bandgap regulator v dd v bb1 + logic supply v reg cp1 cp cp2 load supply 1 gate drive sleep mode control logic phase sync rect mode sync rect disable mode programmable pwm timer sense 1 r s1 fixed off blank decay enable 1 osc clock data strobe reference buffer & divider out 1a out 1b ref 1 v ref c s1 programmable pwm timer fixed off blank decay gate drive dwg. fp-048-1 control logic phase enable sync rect mode sync rect disable pwm mode int pwm mode ext sense 2 r s2 enable 2 reference buffer & divider out 2a out 2b ref 2 v ref2 c s2 v bb2 load supply 2 + serial port charge pump to pwm timer zero current detect current sense zero current detect current sense
dmos dual full-bridge pwm motor driver a3974 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a = +25c, v bb = 50 v, v dd = 5.0 v, f pwm < 50 khz (unless otherwise noted). limits characteristic symbol test conditions min. typ. max. units output drivers load supply voltage range v bb operating 15 ? 50 v during sleep mode 0 ? 50 v output leakage current i dss v out = v bb ? <1.0 20 a v out = 0 v ? <-1.0 -20 a output on resistance r ds(on) source driver, i out = -1.5 a ? 0.5 0.55 sink driver, i out = 1.5 a ? 0.315 0.35 body diode forward voltage v f source diode, i f = 1.5 a ? ? 1.2 v sink diode, i f = 1.5 a ? ? 1.2 v load supply current i bb f pwm < 50 khz ? 4.0 7.0 ma charge pump on, outputs disabled ? 2.0 5.0 ma sleep or idle mode ? ? 20 a control logic logic supply voltage range v dd operating 4.5 5.0 5.5 v logic input voltage v in(1) 2.0 ? ? v v in(0) ? ? 0.8 v logic input current i in(1) v in = 2.0 v ? <1.0 20 a (except enable) i in(0) v in = 0.8 v ? <1.0 20 a enable input current i en(1) v en = 2.0 v ? 40 100 a i en(0) v en = 0.8 v ? 16 30 a osc input frequency f osc 2.9 ? 6.1 mhz osc input duty cycle ? 40 ? 60 % osc input hysterisis v in 200 ? 400 mv reference input voltage range v ref operating 0 ? 2.6 v continued next page ...
dmos dual full-bridge pwm motor driver a3974 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com limits characteristic symbol test conditions min. typ. max. units control logic (continued) reference input current i ref v ref = 2.6 v ? ? 1.0 a reference input offset voltage v io ? 10 ? mv reference divider ratio v ref /v s d16 = 1 ? 10 ? ? d16 = 0 ? 5.0 ? ? gain (g m ) error (note 3) e g v ref = 2.6 v, d16 = 0 ? 0 4.0 % v ref = 0.5 v, d16 = 0 ? 0 14 % v ref = 2.6 v, d16 = 1 ? 0 4.0 % v ref = 0.5 v, d16 = 1 ? 0 10 % propagation delay time t pd 50% to 90%: pwm change to source on 600 750 1000 ns pwm change to source off 50 150 350 ns pwm change to sink on 600 750 1000 ns pwm change to sink off 50 150 350 ns crossover delay time t cod sr enabled 300 600 1000 ns thermal shutdown temperature t j ? 165 ? c thermal shutdown hysteresis t j ? 15 ? c uvlo enable threshold v uvlo increasing v dd 3.9 4.2 4.45 v uvlo hysteresis v uvlo 0.05 0.10 ? v logic supply current i dd f pwm < 50 khz ? ? 10 ma outputs off ? ? 8.0 ma idle mode (d18 = 1, d19 = 0) ? ? 1.5 ma sleep mode (inputs below 0.5 v) ? ? 100 a notes: 1. typical data is for design information only. 2. negative current is de ned as coming out of (sourcing) the speci ed device terminal. 3. e g = [(v ref /range) - v s ]/(v ref /range). electrical characteristics at t a = +25c, v bb = 50 v, v dd = 5.0 v, f pwm < 50 khz (unless otherwise noted), continued.
dmos dual full-bridge pwm motor driver a3974 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com serial interface. the a3974sed is controlled via a 3-wire (clock, data,strobe) serial port. the programmable functions allow maximum exibility in con guring the pwm to the mo- tor drive requirements. the serial data is written as two 20-bit words: 1 bit to select the word and 19 bits of data. the data is clocked in starting with d19. word 0 bit assignments select word 0 (d18 = 0) bit function d0 bridge 1 blank time lsb d1 bridge 1 blank time msb d2 bridge 1 off-time lsb d3 bridge 1 off-time bit 1 d4 bridge 1 off-time bit 2 d5 bridge 1 off-time bit 3 d6 bridge 1 off-time msb d7 bridge 1 fast-decay time bit lsb d8 bridge 1 fast-decay time bit 1 d9 bridge 1 fast-decay time bit 2 d10 bridge 1 fast-decay time msb d11 bridge 1 sync. rect. control d12 bridge 1 sync. rect. control d13 bridge 1 external pwm mode d14 bridge 1 enable d15 bridge 1 phase d16 bridge 1 reference range select d17 bridge 1 internal pwm mode d18 word select = 0 d19 test mode d0 ? d1 blank time. the current-sense comparator is blanked when any output driver is switched on, according to the table below. f osc is the oscillator input frequency. d1 d0 blank time 0 0 4/f osc 0 1 6/f osc 1 0 12/f osc 1 1 24/f osc d2 ? d6 fixed off time. this ve-bit word sets the xed off-time for the internal pwm control circuitry. the off-time is de ned by t off =(8 [1 + n]/f osc ) - 1/f osc where n = 0 .... 31 for example, with an oscillator frequency of 4 mhz, the xed off-time will be adjustable from 1.75 s to 63.75 s in incre- ments of 2 s. d7 ? d10 fast decay time. this four-bit word sets the fast- decay portion of the xed off-time for the internal pwm control circuitry. this will only have impact if mixed-decay mode is selected (via bit d17). for t fd > t off , the device will effectively operate in fast-decay mode. the fast-decay portion is de ned by t fd = (8[1 + n]/f osc ] - 1/f osc where n = 0 .... 15 for example, with an oscillator frequency of 4 mhz, the fast- decay time will be adjustable from 1.75 s to 31.75 s in incre- ments of 2 s. d11 ? d12 synchronous recti cation. d12 d11 synchronous recti er 0 0 disabled 0 1 low side only 1 0 active 1 1 passive the different modes of operation are described in the synchro- nous recti cation section of the functional description. d13 external pwm decay mode. this bit determines the current-decay mode when using enable chopping for external pwm current control. d13 mode 0 fast 1 slow functional description continued next page ...
dmos dual full-bridge pwm motor driver a3974 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description (continued) continued next page ... d14 enable logic. this bit, in conjuction with enable, determines if the output drivers are in the chopped or on state. enable1 d14 mode 0 0 chopped 1 0 on 0 1 on 1 1 chopped d15 phase logic. this bit determines if the device is operat- ing in the forward or reverse state. d15 state out a out b 0 reverse l h 1 forward h l d16 g m range select. this bit determines if v ref is divided by 5 or 10. d16 divider 0 10 1 5 d17 bridge 2 mode. this bit determines slow or mixed decay for internal current-control operation. d17 decay mode 0 mixed 1 slow d19 test mode. this bit is reserved for testing and should never be changed by the user. default (low) operates the device in normal mode. word 1 bit assignments select word 1 (d18 = 1) bit function d0 bridge 2 blank time lsb d1 bridge 2 blank time msb d2 bridge 2 off-time lsb d3 bridge 2 off-time bit 1 d4 bridge 2 off-time bit 2 d5 bridge 2 off-time bit 3 d6 bridge 2 off-time msb d7 bridge 2 fast-decay time bit lsb d8 bridge 2 fast-decay time bit 1 d9 bridge 2 fast-decay time bit 2 d10 bridge 2 fast-decay time bit msb d11 bridge 2 sync. rect. control d12 bridge 2 sync. rect. control d13 bridge 2 external pwm mode d14 bridge 2 enable d15 bridge 2 phase d16 bridge 2 reference range select d17 bridge 2 internal pwm mode d18 word select = 1 d19 idle mode d0 - d17. identical de nitions as word 0, with word 1 selected. data is written to full bridge 2. d19 idle mode. the device can be placed in a low-power ?idle? mode by writing a ?0? to d19. the outputs will be dis- abled, the charge pump will be turned off, and the device will draw a lower load supply currrent. the undervoltage monitor circuit will remain active. d19 should be programmed high for 1 ms before attempting to enable any output driver.
dmos dual full-bridge pwm motor driver a3974 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com v reg . this internally generated supply voltage is used to oper- ate the sink-side dmos outputs. v reg is internally monitored and in the case of a fault condition, the outputs of the device are disabled. the v reg terminal should be decoupled with a 0.22 f capacitor to ground. charge pump. the charge pump is used to generate a supply voltage greater than v bb to drive the source-side dmos gates. a 0.22 f ceramic capacitor should be connected between cp1 and cp2 for pumping purposes. a 0.22 f ceramic capacitor should be connected between v cp and v bb to act as a reservoir to run the high-side dmos devices. the cp voltage is internally monitored and in the case of a fault condition, the outputs of the device are disabled. shutdown. in the event of a fault due to excessive junction temperature, or low voltage on cp or v reg , the outputs of the device are disabled until the fault condition is removed. at power up, or in the event of low v dd , the uvlo circuit disables the drivers and resets the data in the serial port to all zeros. current regulation. load current is regulated by an inter- nal xed off-time pwm control circuit. when the outputs of the dmos h-bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (r s ), the applied analog reference voltage (v ref ), and serial data bit d16: when d16 = 0 ....................... i trip = v ref /10r s when d16 = 1 ....................... i trip = v ref /5r s at the trip point, the sense comparator resets the source-enable latch, turning off the source driver (except in the case of low- side only mode where the sink driver is turned off). the load inductance then causes the current to recirculate for the serial- port programmed xed off-time period. the current path during recirculation is determined by the con guration of slow/mixed- decay mode (d17) and the synchronous recti cation control bits (d11 and d12). sleep mode. the input terminal sleep is dedicated to putting the device into a minimum current draw mode. when asserted functional description (continued) low, the serial port will be reset to all zeros and all circuits will be disabled. pwm timer function. the pwm timer is programmable via the serial port (bits d2 ? d10) to provide xed off-time pwm signals to the control circuitry. in mixed current-decay mode, the rst portion of the off time operates in fast decay, until the fast-decay time count is reached (serial bits d7 ? d10), followed by slow decay for the rest of the off-time period (bits d2 ? d6). if the fast-decay time is set longer than the off-time, the device effectively operates in fast-decay mode. bit d17 selects mixed or slow decay. synchronous recti cation. when a pwm off cycle is trig- gered, either by an enable chop command or internal xed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. after a short crossover delay, the a3974 synchronous recti cation feature will turn on the appropriate mosfet (or pair of mosfets for the mixed decay portion of the off-time) during the current decay and ef- fectively short out the body diodes with the low r ds(on) driver. this will lower power dissipation signi cantly and can eliminate the need for external schottky diodes. synchronous recti cation can be con gured in active mode, pas- sive mode, low side only, or disabled via the serial port (bits d11 and d12). the active mode prevents reversal of load current by turning off synchronous recti cation when a zero current level is detected. passive mode will allow reversal of current but will turn off the synchronous recti er circuit if the load current inver- sion ramps up to the current limit set by v ref /10r s (when d16 = 0) or v ref /5r s (when d16 = 1). low side only mode will switch the low-side mosfets on dur- ing the off time to short out the current path through the mos- fet body diode. with this setting, the high-side mosfets will not synchronously rectify so four external diodes from output to supply are recommended. this mode is intended for use with high-power applications where it is desired to save the expense of two external diodes per bridge. in this mode, the sink-side mosfets are chopped during the pwm off time. in all other cases, the source-side mosfets are chopped in response to a pwm off command.
dmos dual full-bridge pwm motor driver a3974 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com current sensing. to minimize inaccuracies in sensing the i trip current level caused by ground-trace ir drops, the sense resistor should have an independent ground return to a ground terminal of the device. for low-value sense resistors, the ir drops in the pcb sense traces of the resistor can be signi cant and should be taken into account. the use of sockets should be avoided as they can introduce variation in r s due to their contact resistance. the maximum value of r s is given as r s = 0.5/i tripmax . braking. the braking function is implemented by driving the device in slow-decay mode via serial port bit d13, enabling synchronous recti cation via bits d11 and d12, and applying an enable chop command with the combination of d14 and the enable input terminal. because it is possible to drive current in both directions through the dmos switches, this con gura- tion effectively shorts out the motor-generated bemf as long as the enable chop mode is asserted. it is important to note that the internal pwm current-control circuit will not limit the cur- rent when braking, because the current does not ow through the sense resistor. the maximum brake current can be approximated by v bemf /r l . care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situ- ations of high speed and high inertial loads. a. minimum data setup time .........................................15 ns b. minimum data hold time ...........................................10 ns c. minimum setup strobe to clock rising edge ............50 ns d. minimum clock high pulse width .............................50 ns e. minimum clock low pulse width ..............................50 ns f. minimum setup clock rising edge to strobe .............50 ns g. minimum strobe pulse width .....................................50 ns applications information thermal protection . circuitry turns off all drivers when the junction temperature reaches 165c typically. it is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. thermal shutdown has a hysteresis of approximately 15c. layout. the printed wiring board should use a heavy ground plane. for optimum electrical and thermal performance, the driver should be soldered directly onto the board. the ground side of r s should have an individual path to a ground terminal of the device. this path should be as short as is possible physically and should not have any other components connected to it. the load supply terminal, v bb , should be decoupled with an electro- lytic capacitor (>47 f is recommended) placed as close to the device as is possible. serial port write timing operation. data is clocked into shift register on the rising edge of clock signal. normally, strobe will be held high, and only will be brought low to initiate a write cycle. refer to diagram below and speci cation table for timing requirements.
dmos dual full-bridge pwm motor driver a3974 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list terminal name terminal description terminal number gnd power and logic ground terminals 1, 2 sense 1 sense resistor terminal for bridge 1 3 nc no (internal) connection 4, 5 out 1a dmos h-bridge 1 ? output a 6 nc no (internal) connection 7 strobe logic input for serial interface 8 clock logic input for serial interface 9 data logic input for serial interface 10 gnd power and logic ground terminals 11, 12, 13 ref 1 g m reference input voltage ? bridge 1 14 ref 2 g m reference input voltage ? bridge 2 15 logic supply v dd , the low voltage (typically 5 v) supply 16 nc no (internal) connection 17 out 2a dmos h-bridge 2 ? output a 18 nc no (internal) connection 19, 20 sense 2 sense resistor pin for bridge 2 21 gnd power and logic ground terminals 22, 23, 24 load supply 2 v bb2 , the high current, 20 v to 50 v, supply for bridge 2 25 enable 2 logic input for bridge 2 ? enable control 26 nc no (internal) connection 27 out 2b dmos h-bridge 2 ? output b 28 nc no (internal) connection 29 v reg regulator decoupling capacitor (typ. 0.22 f) 30 sleep logic input for sleep mode 31 osc logic-level oscillator (square wave) input 32 gnd power and logic ground terminals 33, 34, 35 cp reservoir capacitor (typically 0.22 f) 36 cp1 & cp2 the charge pump capacitor (typically 0.22 f) 37 & 38 nc no (internal) connection 39 out 1b dmos h-bridge 1 ? output b 40 nc no (internal) connection 41 enable 1 logic input for bridge 1 ? enable control 42 load supply 1 v bb1 , the high current, 20 v to 50 v, supply for bridge 1 43 gnd power and logic ground terminals 44
dmos dual full-bridge pwm motor driver a3974 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 2144 a internally fused pins 44, 1 and 2; 11-13; 22-24; and 33-35 dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area for reference only (reference jedec ms-018 ac) dimensions in millimeters c seating plane 0.51 4.57 max 16.59 0.08 16.59 0.08 7.75 0.36 7.75 0.36 7.75 0.36 7.75 0.36 c 0.10 44x 0.74 0.08 17.53 0.13 17.53 0.13 1.27 0.43 0.10 package eb, 44-pin plcc copyright ?2001-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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